1. Field of the Invention
The present invention relates generally to integrated circuit clocking and, more specifically, to distributing a clock throughout an integrated circuit system.
2. Background Information
An issue facing the integrated circuit industry today is the problem of distributing clock signals throughout integrated circuit systems and integrated circuit dice with low clock skew. Clock skew is the difference in arrival times of clock edges to different parts of the system. Synchronous digital logic requires precise clocks for the latching of data. Ideal synchronous logic relies on clocks arriving simultaneously to all circuits in the system. Clock skew reduces the maximum operating frequency of the system as the system has to be designed for worst case skew for it to operate reliably. The principle cause of clock skew in the global clock distribution of an integrated circuit system is the variation in the routing impedance of the clock distribution within the system. Hence clock skew arises within an individual integrated circuit die even with an equal length clock distribution network such as an H-Tree. A good rule of thumb in the industry is that clock skew budget is approximately 10% of the cycle time. Hence for a 1 GHz clock frequency, which corresponds to a 1 ns cycle time, the tolerable clock skew is less than or equal to 100 ps. As VLSI clock frequencies increase beyond 1 GHz, the requirement on the clock skew becomes even more challenging.
FIG. 1 is a block diagram of a system 101 having a plurality of dice including a processor 117 communicating with other dice including chip set 115 and memory 113. Input/output communications among processor 117, chip set 115 and memory 113 are clocked using external crystal oscillator 103. A clock signal 121 is generated by using external crystal oscillator 103, which is received by phase lock loop 105. Phase lock loop 105 generates a clock signal 123, which is received by the buffer circuits 107, 109 and 111. Buffer circuits 107, 109 and 111 generate clock signals 125, 127 and 129, which are all in phase with each other and are used to drive memory 113, chip set 115 and processor 117, respectively. A clock input of processor 117 is fed back to divide by N circuit 119 back into phase lock loop 105 to achieve the system level phase locking and clocking for processor 117, chip set 115 and memory 113.
FIG. 2 is a block diagram of some of the internal clocking elements of processor 117, which is illustrated in FIG. 1. As shown in FIG. 2, clock signal 129 is received by a phase lock loop circuit 201, which generates a clock signal 209 received by a synchronizer and divider 203. Synchronizer and divider 203 generates a divided clock output 210 and a clock signal 211, which is used to clock the logic of processor 117 through electrically routed H-tree 205, which will be described in greater detail below. Electrically routed H-tree 205 includes an output which is logically-AND'ed with divided clock output 210 of synchronizer 203 using logical-AND gate 207. An output of logical-AND gate 207 is fed back into phase lock loop 201. By using the clocking circuitry illustrated in FIG. 2, digital logic and input/output functions of processor 117 are phase locked and clocked for operation.
FIG. 3 is a diagram of the electrically routed H-tree 205 of FIG. 2. In today's global clock distribution networks, clock skew may be controlled with the use of electrical hierarchical H-trees. FIG. 3 is a diagram illustrating such a hierarchical H-tree clock distribution network 205 that is implemented in high-speed integrated circuits to reduce or eliminate a clock skew effect. As shown in FIG. 3 a clock signal 211 is used to drive electrical H-tree network 205 at the center node 301. It is noted that clock signal 211 is typically generated by a very large driver in order to provide sufficient drive to H-tree network 205, which typically has a large capacitance in today's complex high speed integrated circuits. As can be observed in FIG. 3, the clock pads of the "H" found between nodes 303A, 303B, 303C and 303D have equal lengths between center node 301 and each of the peripheral points of the "H" at nodes 303A, 303B, 303C and 303D. Therefore, assuming a uniform propagation delay of clock signal 211 per unit length of the H-tree network 205, there should be no clock skew between the clock signal 211 supplied to nodes 303A, 303B, 303C and 303D.
FIG. 3 further illustrates H-tree network 205 taken to another hierarchical level with a "H" coupled to each respective peripheral node of the first level "H." Accordingly, every peripheral node 303A-D is an equal distance from node 303A. Every peripheral node 307A-D is an equal distance from node 303B. Every peripheral node 309A-D is an equal distance from node 303C. Every peripheral node 311A-D is an equal distance from node 303D. Therefore, the clock paths to all of the peripheral clock receiver nodes 305A-D, 307A-D, 309A-D and 311A-D are an equal distance from the clock driver of clock signal 211 and therefore should have no clock skew between them because the clock delay from the clock driver of clock signal 211 should be equal to all peripheral nodes of the H-tree network 205. Thus, each clock receiver node 305A-D, 307A-D, 309A-D and 311A-D can be configured to act as a receiving station for clock signal 211 and service the clocking requirements of an area of the integrated circuit near the node with negligible clock skew with reference to the other similarly configured nodes of the H-tree network 205.
As integrated circuits continue to become larger, more complex and run at higher frequencies, clock skew continues to be a challenging issue, even with an electrical H-tree network 205 since H-tree network 205 clock lines do not always have uniform characteristic impedance. As a result, there may be a non-uniform propagation delay of a clock signal 211 travelling through the paths of H-tree network 205 even though clock receiver nodes 305A-D, 307A-D, 309A-D and 311A-D are an equal distance from the clock driver of clock signal 211. Consequently, there is an unpredictable clock skew at the end points of the H-tree clock distribution network 205.
In addition to clock skew, the clock distribution on the die consumes valuable routing resources in integrated circuits that could be better used for signals and thereby improve signal route ability. An additional concern integrated circuit designers must consider is that known global clock distribution networks also consume an increasing amount of integrated circuit die area as well as power.